module TrafficLight(start, rst, clk, red, yellow, green,cnt);
	input			start;
	input			rst;
	input			clk;
	output	reg		red;
	output	reg		yellow;
	output	reg		green;
	wire			next_state;
	reg				current_state;
	reg				cnt_up;
	output	reg		[2:0]	cnt;
	
	assign next_state = (start & rst) ;
	
	//D触发器
	always @(posedge clk or negedge rst) begin
		if(!rst)
			current_state <= 0;
		else if(current_state == 1)
			current_state = 1;
		else
			current_state <= next_state;
	end
	
	//计数器
	always @(posedge clk or negedge rst) begin
		if((!rst)|(!current_state)) begin
			cnt <= 0;
			cnt_up <= 0;
		end
		else if(cnt == 4) begin
			cnt <= 0;
			current_state <= 0;
		end
		else begin
			cnt <= cnt + 1;
			cnt_up <= 0;
		end
	end
	
	//输出解码器
	always @(cnt) begin
		case(cnt)
			0: begin red=1; yellow=0; green=0; end
			1: begin red=0; yellow=1; green=0; end
			2: begin red=0; yellow=0; green=1; end
			3: begin red=0; yellow=0; green=1; end
			4: begin red=0; yellow=0; green=1; end
			default: begin red=0; yellow=0; green=0; end
		endcase
	end
	
endmodule